library IEEE;
use IEEE.std_logic_1164.all;

entity testbench_uart_controller is
end testbench_uart_controller;

architecture test of testbench_uart_controller is

	constant PERIOD : time := 10 ns;

	component uart_controller
		port (
			d_i		: in  std_logic_vector(7 downto 0);
			tx_i 	: in  std_logic;
			reset_i	: in  std_logic;
			nclk_i	: in  std_logic;
			txd_o	: out std_logic
		);
	end component;

	signal d		: std_logic_vector(7 downto 0);
	signal tx 		: std_logic;
	signal reset	: std_logic;
	signal nclk		: std_logic;
	signal txd		: std_logic;

begin

	uart_controller_inst : uart_controller
		port map (
			d_i		=> d,
			tx_i 	=> tx,
			reset_i	=> reset,
			nclk_i	=> nclk,
			txd_o	=> txd
		);

	gen_clk : process
	begin
		nclk <= '0';
		wait for PERIOD/2;
		nclk <= '1';
		wait for PERIOD/2;
	end process;

	gen_test : process
	begin
		wait for 5*PERIOD;

		d		<= X"00";
		tx 		<= '0';
		reset	<= '1';
		
		wait for PERIOD;

		d		<= X"54";
		tx 		<= '1';
		reset	<= '0';

		wait for PERIOD;

		tx 		<= '0';

		wait;
	end process;

end test;
